Adder-accumulator Cells in RSFQ Logic

IEEE Transactions on Applied Superconductivity

Volumn 5, Issue 2, 1995, Pages 3006-3009

  Martinet, Stephen S ^a   Brock, Darren K ^a   Feldman, Marc J ^a   Bocko, Mark F ^a  

^a UNIVERSITY OF ROCHESTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BINARY SEQUENCES; DIGITAL FILTERS; DIGITAL SIGNAL PROCESSING; FABRICATION; LOGIC DEVICES;

ADDER ACCUMULATOR CELLS; ARITHMETIC UNIT; ITERATIVE NETWORKS; RAPID SINGLE FLUX QUANTUM LOGIC;

LOGIC CIRCUITS;

EID: 0029326158     PISSN: 10518223     EISSN: 15582515     Source Type: Journal    
DOI: 10.1109/77.403224     Document Type: Article

References (5)

1. K.K. Likharev and V.K. Semenov, “RSFQ Logic/Memory Family: A New Josephson Junction Technology for Sub-Terahretz-Clock-Frequency Digital Systems,” IEEE Trans. Appl. Supercond., vol. 1, pp. 3-28, March 1991.
2. S.S. Martinet and M.F. Bocko, “Simulation and Optimization of Binary Full-adder Cells in RSFQ Logic,” IEEE Trans. Appl. Suoercond., vol. 3, pp. 2720-2723, March, 1993.
3. K. Gaj, E.G. Friedman and M.J. Feldman, “A Clock Distribution Scheme for Large RSFQ Circuits,” submitted concurrently to IEEE Trans. Appl. Suoercond., ASC'94.
4. S.V. Polonsky, et al, “New RSFQ Circuits,” IEEE Trans. Appl. Supercond., vol. 3, pp. 2566-2577, March, 1993.
5. Circuits fabricated by HYPRES, Inc., 175 Clearbrook Road, Elmsford, NY, 10523, (914) 592-1190.