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Volumn 43, Issue 12, 1995, Pages
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Delay effects rule in deep-submicron ICs
a
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Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
CAPACITANCE;
ELECTRIC LOADS;
ELECTRIC WIRING;
INTEGRATED CIRCUIT LAYOUT;
INTEGRATED CIRCUITS;
LOGIC GATES;
MATHEMATICAL MODELS;
RESONANT CIRCUITS;
DELAY EFFECTS;
INTERCONNECT DELAYS;
LUMPED LOAD MODEL;
ELECTRIC DELAY LINES;
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EID: 0029323260
PISSN: 00134872
EISSN: None
Source Type: Trade Journal
DOI: None Document Type: Article |
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Times cited : (2)
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References (0)
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