Macro Pipelining Based Scheduling on High Performance Heterogeneous Multiprocessor Systems

IEEE Transactions on Signal Processing

Volumn 43, Issue 6, 1995, Pages 1468-1484

  Banerjee, Sati ^a   Hamada, Takeo ^b   Chau, Paul M ^c   Fellman, Ronald D ^c  

^a General Instrument Corporation ^*  (United States)

^b FUJITSU LABORATORIES LTD   (Japan)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; ITERATIVE METHODS; MULTIPROCESSING SYSTEMS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; ROBUSTNESS (CONTROL SYSTEMS); SCHEDULING;

HETEROGENEOUS MULTIPROCESSOR SYSTEMS; LINEAR INTERPROCESSOR COMMUNICATION; MACRO PIPELINING BASED SCHEDULING; RATIO CUT PARTITIONING TECHNIQUE; SCHEDULING ALGORITHMS; TIME AXIS LABELING TECHNIQUE;

PIPELINE PROCESSING SYSTEMS;

EID: 0029323195     PISSN: 1053587X     EISSN: 19410476     Source Type: Journal    
DOI: 10.1109/78.388859     Document Type: Article

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