An Asynchronous Distributed Approach for the Simulation of Behavior-Level Models on Parallel Processors

IEEE Transactions on Parallel and Distributed Systems

Volumn 6, Issue 6, 1995, Pages 639-652

  Yu, Meng Lin ^b  

^a ARIZONA STATE UNIVERSITY   (United States)

^b LUCENT TECHNOLOGIES   (United States)

Author keywords

asynchronous algorithms; Digital systems simula ; Distributed simulation; parallel processors; tion

Indexed keywords

ASYNCHRONOUS DISTRIBUTED ALGORITHMS; BEHAVIOR LEVEL MODELS; DIGITAL DESIGN; DIGITAL SYSTEMS SIMULATION; PARALLEL PROCESSORS; SIGNAL TRANSITIONS;

COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SYSTEM RECOVERY; CONCURRENCY CONTROL; DIGITAL COMPUTERS; DISTRIBUTED COMPUTER SYSTEMS; NETWORK PROTOCOLS; PARALLEL ALGORITHMS; PARALLEL PROCESSING SYSTEMS; PERFORMANCE;

COMPUTER SIMULATION;

EID: 0029322820     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/71.388044     Document Type: Article

References (49)

1. VHDL Language Reference Manual, IEEE Standard 1076, 1989.
2. D. Hill, ADLIB Users Manual. Comput. Syst. Lab., Stanford Univ., CA, Tech. Rep. 177, 1979.
3. C. Seitz, “The cosmic cube,” CACM, pp. 22-23, Jan. 1985.
4. E. DeBenedictis, “Multiprocessor programming with distributed variables,” in Proc. Conf. Hypercube Multiprocessor, Aug. 1985.
5. D. C. Luckham, A. Stanculescu, Y. Huh, and S. Ghosh, “The semantics of timing constructs in hardware description languages,” in Proc. Int. Conf. Comput. Design, pp. 10-14, Oct. 1986.
6. S. Ghosh and M. Yu, “A preemptive scheduling mechanism for accurate behavioral simulation of digital designs,” IEEE Trans. Comput., vol. 38, Nov. 1989.
7. B. Stroustrup, Ed., The C+ + Programming Language. Reading, PA: Addison-Wesley, 1986.
8. M. M. Denneau, “The Yorktown simulation engine,” in Proc. 19th ACM/IEEE DA Conf, 1983, pp. 55-59.
9. J. K. Howard et al., “Introduction to the IBM Los Gatos logic simulation engine,” in Proc. ICCD, Oct. 1983, pp. 580-583.
10. The ZYCAD Logic Evaluator: Product Description, ZYCAD Corp., N. Roseville, MN, 1983.
11. J. Misra, “Distributed discrete-event simulation,” Comput. Surv., vol. 18, no. 1, pp. 39-65, Mar. 1986.
12. K. M. Chandy et al., “Distributed deadlock detection,” ACM Trans. Comput. Syst., vol. 1, no. 2, pp. 144-156, May 1983.
13. L. Lamport, “Time, clocks, and the ordering of events in a distributed system,” CACM, vol. 21, no. 7, pp. 559-565, 1978.
14. J. K. Peacock et al., “Distributed simulation using a network of processors,” Comput. Networks, vol. 3, no. 1, pp. 44-56, 1979.
15. Daisy Megalogician: Product description, Daisy Syst., Mountain View, 1984.
16. M. E. Glazier et al., “ULTIMATE: A hardware logic simulation engine,” in Proc. 20th ACM/IEEE DA Conf., 1984, pp. 336-342.
17. M. Bloom, “Behavior models take the pain out of system simulation,” Comput. Design, pp. 38-46, Feb. 15, 1987.
18. D. Jefferson, “Virtual time,” ACM Trans. Programming Languages, vol. 7, no. 3, pp. 404-425, July 1985.
19. S. Ghosh and M.-L. Yu, “An asynchronous distributed approach for the simulation of behavior-level models on parallel processors,” in Proc. 1988 Int. Conf. Parallel Processing, St. Charles, IL, Aug. 15-19, 1988.
20. K. M. Chandy and J. Misra, “Asynchronous distributed simulation via a sequence of parallel computations,” Commun. ACM, vol. 24, no. 4, pp. 198-206, Apr. 1981.
21. D. A. Reed and A. Malony, “Parallel discrete event simulation: The Chandy-Misra approach,” in Proc. SCS Multiconf. Distrib. Simulation, San Diego, CA, Feb. 3-5, 1988, pp. 8-13.
22. Private communications with K. F. Wong, Dep. Comput. Sci., Washington Univ., St. Louis, MO, June 1988.
23. Private communication with Prof. E. Cerny, Dep. Comput. Sci., Univ. Montreal, Montreal, PQ, Canada, Apr. 1991.
24. J. T. Rayfield and H. F. Silverman, “Operating system and applications of the Armstrong multiprocessor,” IEEE Comput., vol. 21, pp. 38-52, June 1988.
25. P. Agrawal, W. Dally, A. Ezzat, W. Fischer, H. Jagadish, and A. Krishnakumar, “Architecture and design of the MARS hardware accelerator,” in Proc. 24th Design Automation Conf, Miami Beach, FL, June 1987, pp. 101-107.
26. S. Ghosh, “Ada as a hardware description language,” IEEE Design and Test Comput., Feb. 1988.
27. M. Barbacci, D. P. Siewiorek, R. Gordon, R. Howbrigg, and S. Zucker-man, “An architectural research facilityISP descriptions, simulation, and data collection,” in Proc. Nat. Comput. Conf, vol. 46, 1977.
28. R. DeVries, “Reducing null messages in Misras distributed discrete event simulation method,” IEEE Trans. Software Eng., vol. 16, pp. 82-91, Jan. 1990.
29. H.-C. Shih, P. G. Kovijanic, and R. Razdan “A global feedback detection algorithm for VLSI circuits,” in Proc. ICCD, Boston, MA, Sept. 17, 1990, pp. 37-40.
30. S. Davidson and J. Lewandowski, “ESIM/AFSA concurrent architectural level fault simulator,” in Proc. Int. Test Conf, Washington DC, Oct. 1986, pp. 375-383.
31. P. M. Athanas and H. F. Silverman, “The reconfigurable communications architecture of the ARMSTRONG II processor,” Div. Eng., Brown Univ., Providence, RI, LEMS Tech. Rep. 83, Apr. 1991.
32. N. Deo, Graph Theory with Applications to Engineering and Computer Science. Englewood Cliffs, NJ: Prentice-Hall, 1974.
33. E. G. Ulrich, “Exclusive simulation of activity in digital networks,” Commun. ACM, vol. 12, no. 2, pp. 102-110, Feb. 1969.
34. J. Sissler, “Assessing the potential of multi-threaded VHDL simulation,” in VHDL Boot Camp Proc., Fall 93 Conf, San Jose, CA, Oct. 10-13, 1993, pp. 131-136.
35. P. Chawla, H. Carter, D. Barker, and S. Bilik, “Preliminary design and analysis of a hardware accelerator for VHDL simulation,” in VHDL Boot Camp Proc., Fall 93 Conf, San Jose, CA, Oct. 10-13, 1993, pp. 267-279.
36. P. J. Ashden, H. Detmold and W. S. McKeen, “Parallel execution of VHDL models,” Dep. Comput. Sci., Univ. Adelaide, Australia, Tech. Rep. 93-01.
37. M. L. Bailey, “A time-based model for investigating parallel logic-level simulation,” IEEE Trans. Comput.-Aided Design, vol. 11, pp. 816-824, July 1992.
38. F. Mattern, “Efficient algorithms for distributed snapshots and global virtual time approximation,” J. Parallel and Distrib. Comput., vol. 18, no. 4, pp. 423-434, 1993.
39. I. F. Akyildiz, L. Chen, S. R. Das, R. Fujimoto, and R. Serfozo, “The effect of memory capacity on time warp performance,” J. Parallel and Distrib. Comput., vol. 18, no. 4, pp. 411-422, 1993.
40. D. M. Nicol and P. Heidelberger, “Optimistic parallel simulation of continuous time Markov chains using uniformization,” J. Parallel and Distrib. Comput., vol. 18, no. 4, pp. 395-410, 1993.
41. T. K. Som and R. G. Sargent, “A new process to processor assignment criterion for reducing rollbacks in optimistic simulation,” J. Parallel and Distrib. Comput., vol. 18, no. 4, pp. 509-515, 1993.
42. C.-P. Wen and K. A. Yelick, “Parallel timing simulation on a distributed memory multiprocessor,” in Proc. ICC AD, Santa Clara, CA, Nov. 7-11, 1993, pp. 131-136.
43. J. V. Briner, J. L. Ellis and G. Kedem, “Breaking the barrier of parallel simulation of digital systems,” in Proc. 28th Design Automat. Conf, San Francisco, CA, June 17-21, 1991.
44. J. S. Steinman, “SPEEDES: Synchronous parallel environment for emulation and discrete event simulation,” in Proc. Fifth Workshop Parallel and Distrib. Simulation (PADS 91), Anaheim, CA, 1991, pp. 95-103 (the Society for Computer Simulation, San Diego, CA).
45. K. M. Chandy and R. Sherman, “The conditional event approach to distributed simulation,” SCS Multiconf. Distrib. Simulation, Tampa, FL, Mar. 28-31, 1989, pp. 93-99.
46. D. West, “Lazy rollback and lazy reevaluation,” M.S. thesis, Univ. Calgary, Jan. 1988.
47. R. M. Fujimoto, “Parallel discrete event simulation,” Commun. ACM, vol. 33, no. 10, 1990, pp. 31-53.
48. L. Soule and A. Gupta, “Characterization of parallelism and deadlocks in distributed digital logic simulation,” in Proc. 26th Design Automat. Conf, June 1989.
49. L. Soule and T. Blank, “Parallel logic simulation on general purpose machines,” in Proc. 25th Design Automat. Conf, June 1988.