Optimization of NbN MVTL Logic Gates for 10 K Operation

IEEE Transactions on Applied Superconductivity

Volumn 5, Issue 2, 1995, Pages 3179-3182

  Leung, Michael ^a   Durand, Dale J ^a   Abelson, Lynn A ^a   Eaton, Larry R ^a   Spargo, John W ^a  

^a NORTHROP GRUMMAN CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL CURRENTS; ELECTRIC CURRENTS; INDUCTANCE MEASUREMENT; LITHOGRAPHY; LOGIC DESIGN; SENSITIVITY ANALYSIS; SQUIDS;

BIAS CURRENT; CURRENT CROWDING; FACTORIAL ANALYSIS; MARGIN MEASUREMENT; MODIFIED VARIABLE THRESHOLD LOGIC GATES;

LOGIC GATES;

EID: 0029321849     PISSN: 10518223     EISSN: 15582515     Source Type: Journal    
DOI: 10.1109/77.403267     Document Type: Article

References (4)

1. D.L. Miller, J.X. Przybysz, J.H. Kang, “Margins and Yields of SFQ Circuits in HTS Materials,” IEEE Transactions on Applied Superconductivity, Vol. 3, No. 1, pp.2728-2731, March 1993.
2. N. Fujimaki, S. Kotani, T. Imamura, S. Hasuo, “Josephson Modified Variable Threshold Logic Gates for use in Ultra-High-Speed LSI,” IEEE Transactions on Electron Devices, Vol. 36, No. 2, pp. 433-446, February 1989.
3. W.H. Chang, “Loop Inductance of a Josephson Junction Interferometer,” J. Appl. Phys., Vol. 51, No. 7, pp.3801-6, July 1980.
4. S.R. Whiteley, “Josephson Junctions in SPICE3,” IEEE Transactions on Magnetics, Vol. 27, No. 2, pp. 2902-5, March 1991.