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Volumn 28, Issue 1-4, 1995, Pages 261-264
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Spatial distribution of interface traps after hot-carrier stress from forward GIDL measurements
a
a
EPFL
(Switzerland)
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Author keywords
[No Author keywords available]
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Indexed keywords
CMOS INTEGRATED CIRCUITS;
COMPUTER SIMULATION;
CURRENT VOLTAGE CHARACTERISTICS;
ELECTRIC CURRENT MEASUREMENT;
HOT CARRIERS;
LEAKAGE CURRENTS;
STRESSES;
CHARGE PUMPING;
GATE INDUCED DRAIN LEAKAGE MEASUREMENTS;
HOT CARRIER STRESS;
INTERFACE TRAPS;
SPATIAL DISTRIBUTION;
TWO DIMENSIONAL SIMULATIONS;
MOSFET DEVICES;
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EID: 0029321704
PISSN: 01679317
EISSN: None
Source Type: Journal
DOI: 10.1016/0167-9317(95)00055-D Document Type: Article |
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Times cited : (7)
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References (5)
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