Fast-Acquisition PLL Synthesizer Using a Parallel N-Stage Cycle Swallower with Low Power Consumption and Low Phase Noise

IEEE Transactions on Vehicular Technology

Volumn 44, Issue 2, 1995, Pages 296-303

  Saba, Takahiko ^a   Mori, Shinsaku ^a   Park, Duk Kyu ^b,c  

^a KEIO UNIVERSITY   (Japan)

^b Ministry of Posts and Telecommunications   (Japan)

^c Department of Information and Communication Engineering Mok Won University ^*  (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

FREQUENCY SWITCHING; LOW PHASE NOISE; LOW POWER CONSUMPTION; N STAGE CYCLE SWALLOWER; PRESCALAR;

ELECTRIC POWER SUPPLIES TO APPARATUS; FREQUENCY HOPPING; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; SWITCHING;

FREQUENCY SYNTHESIZERS;

EID: 0029310075     PISSN: 00189545     EISSN: 19399359     Source Type: Journal    
DOI: 10.1109/25.385922     Document Type: Article

References (19)

1. W. C. Y. Lee, “Overview of cellular CDMA,” IEEE Trans. Vehic. Technol., vol. 40, pp. 291–302, May 1991.
2. J. Tiemey, C. M. Radar, and B. Gold, “A digital frequency synthesizer,” IEEE Trans. Audio Electroacoust., vol. AU-19, pp. 48–57, Mar. 1971.
3. V. Reinhardt, K. Gould, K. McNab, and M. Bustamante, “A short survey of frequency synthesizer techniques,” in Proc. IEEE 40th Annu. Frequency Control Symp., Sept. 1986, pp. 355–365.
4. W. F. Egan, Frequency Synthesis by Phase Lock. New York: Wiley, 1981.
5. U. L. Rohde, Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ: Prentice-Hall, 1983.
6. V. Manassewitsch, Frequency Synthesizers Theory and Design: Third Edition. New York: Wiley, 1987.
7. J. R. Alexovich and R. M. Gagliardi, “Effect of PLL frequency synthesizer in FSK frequency-hopped communications,” IEEE Trans. Commun., vol. 37, pp. 268–176, Mar. 1989.
8. S. Saito, Y. Tarusawa, and H. Suzuki, “State-preserving intermittently locked loop (SPILL) frequency synthesizer for portable radio,” IEEE Trans. Microwave Theory Tech., vol. 37, pp. 1898–1903, Dec. 1989.
9. A. Kajiwara and M. Nakagawa, “A new PLL frequency synthesizer with high switching speed,” IEEE Trans. Vehic. Technol., vol. 41, pp. 407–4013, Nov. 1992.
10. K. Seki, M. Morimura, and S. Kato, “High resolution and fast frequency settling PLL synthesizer,” IEICE Trans. Commun., E75-B, no. 8, pp. 739–746, Aug. 1992.
11. D. K. Park and S. Mori, “Fast acquisition frequency synthesizer with n-stage novel type cycle swallowers,” in Proc. IEEE ICC'92, June 1992, pp. 496–500.
12. D. K. Park and S. Mori, “Fast acquisition frequency synthesizer with multi-stage cycle swallowers,” Trans. IEICE. vol. J75-B-II, pp. 515–523, Aug. 1992 (in Japanese).
13. D. K. Park and S. Mori, “Fast acquisition frequency synthesizer with n-stage cycle swallowers, which switched the time constants of the loop filter,” in Proc. 1992 Joint Tech. Conf. Circuits/Syst. Computer and Commun., July 1992, pp. 168–173.
14. T. Saba, D. K. Park, and S. Mori, “Fast acquisition PLL frequency synthesizer with improved N-stage cycle swallower,” in Proc. IEEE Pacific Rim Conf.'93, May 1993, pp. 77–80.
15. The Ordinance for Regulating Radio Equipment of Japan. 1993.
16. S. Saito, T. Takada, and N. Kato, “A 5-mA 1-GHz GaAs dual-modulus prescalar IC,” IEEE J. Solid-State Circuits, vol. 21, pp. 538–543, Aug. 1989.
17. F. M. Gardner, “Charge-pump phase-lock loops,” IEEE Trans. Commun., vol. COM-28, pp. 1849–1858, Nov. 1980.
18. H. M. Berlin, The Phase-Locked Loop Bugbook, with Experiments. E & L Instruments, Inc., 1978.
19. J. Smith, Modern Communication Circuits. New York: McGraw-Hill, 1986.