Semiconductor Yield Improvement: Results and Best Practices

IEEE Transactions on Semiconductor Manufacturing

Volumn 8, Issue 2, 1995, Pages 103-109

  Cunningham, Sean P ^a   Spanos, Costas J ^a   Voros, Katalin ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSEMBLY; COMPUTER AIDED MANUFACTURING; ECONOMICS; FAILURE ANALYSIS; INDUSTRIAL MANAGEMENT; QUALITY CONTROL; RESEARCH AND DEVELOPMENT MANAGEMENT; SEMICONDUCTOR DEVICE TESTING; STATISTICAL PROCESS CONTROL;

ADVANCED MANUFACTURING TECHNOLOGY; DIE YIELD; FINAL TEST YIELD; LINE YIELD; PARTICLE CONTROL; WAFER FABRICATION; YIELD IMPROVEMENT;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0029304803     PISSN: 08946507     EISSN: 15582345     Source Type: Journal    
DOI: 10.1109/66.382273     Document Type: Article

References (2)

1. “The competitive semiconductor manufacturing survey: First report on results of the main phase,” R. C. Leachman Ed., Competitive Semiconductor Manufacturing Program, ESRC/CSM-02. Univ. California, Berkeley, 1993.
2. J. A. Cunningham, “The use and evaluation of yield models in integrated circuit manufacturing,” IEEE Trans. Semicond. Manufact., vao. 3, pp. 60-71, Aug. 1990.