-
1
-
-
0022594798
-
Attacking the problem of minimizing channel density
-
H. Cai and P. Dewilde, “Attacking the problem of minimizing channel density,” in Proc. Int. Symp. Circuits Syst., 1986, pp. 353–356.
-
(1986)
Proc. Int. Symp. Circuits Syst.
, pp. 353-356
-
-
Cai, H.1
Dewilde, P.2
-
2
-
-
0025594168
-
Global routing based on steiner min-max trees
-
Dec.
-
C. Chiang, M. Sarrafzadeh, and C. K. Wong, “Global routing based on steiner min-max trees,” IEEE Trans. Computer-Aided Design, vol. 9, no. 12, pp. 131–1325, Dec. 1990.
-
(1990)
IEEE Trans. Computer-Aided Design
, vol.9
, Issue.12
, pp. 131-1325
-
-
Chiang, C.1
Sarrafzadeh, M.2
Wong, C.K.3
-
3
-
-
0020890408
-
BBL: A building block layout system for custom chip design
-
N. P. Chen, C. P. Hsu, E. S. Kuh, C. C. Chen, and M. Takahashi, “BBL: A building block layout system for custom chip design,” in Proc. Int. Conf. Computer-Aided Design, 1983, pp. 40-41.
-
(1983)
Proc. Int. Conf. Computer-Aided Design
, pp. 40-41
-
-
Chen, N.P.1
Hsu, C.P.2
Kuh, E.S.3
Chen, C.C.4
Takahashi, M.5
-
4
-
-
0348124642
-
Routing region definition and ordering scheme for building block layout
-
July
-
W. M. Dai, T. Asano, and E. S. Kuh, “Routing region definition and ordering scheme for building block layout,” IEEE Trans. Computer- Aided Design, vol. CAD-4, no. 3, pp. 189–197, July 1985.
-
(1985)
IEEE Trans. Computer- Aided Design
, vol.CAD-4
, Issue.3
, pp. 189-197
-
-
Dai, W.M.1
Asano, T.2
Kuh, E.S.3
-
5
-
-
0024905154
-
On global wire ordering for macro-cell routing
-
P. Groenveld, “On global wire ordering for macro-cell routing,” Proc. Design Automation Conf., 1989, pp. 155–160.
-
(1989)
Proc. Design Automation Conf.
, pp. 155-160
-
-
Groenveld, P.1
-
6
-
-
0025693998
-
Third-generation architecture boosts speed and density of field-programmable gate array
-
H. C. Hsieh et al., “Third-generation architecture boosts speed and density of field-programmable gate array,” Proc. Custom Integrated Circuits Conf., 1990, pp. 31. 2.1–31.2.7.
-
(1990)
Proc. Custom Integrated Circuits Conf.
, pp. 31.2.1-31.2.7
-
-
Hsieh, H.C.1
-
8
-
-
0018296470
-
A min-cut placement algorithm for general cell assemblies based on a graph representation
-
June
-
U. Lauther, “A min-cut placement algorithm for general cell assemblies based on a graph representation,” in Proc. 16th Design Automation Conf., June 1987, pp. 1-10.
-
(1987)
Proc. 16th Design Automation Conf.
, pp. 1-10
-
-
Lauther, U.1
-
10
-
-
84933375823
-
-
a chapter in “The impact of layer assignment methods on layout algorithms for integrated circuits, Ph.D. dissertation, Dept. of Elec. Eng., M.I.T., Cambridge, MA, Aug.
-
R. Pinter, “Optimal routing in rectilinear channel,” a chapter in “The impact of layer assignment methods on layout algorithms for integrated circuits, Ph.D. dissertation, Dept. of Elec. Eng., M.I.T., Cambridge, MA, Aug. 1982.
-
(1982)
Optimal routing in rectilinear channel
-
-
Pinter, R.1
-
11
-
-
0024714519
-
A new approach to topological via minimization
-
Aug.
-
M. Sarrafzadeh and D. T. Lee, “A new approach to topological via minimization,” IEEE Trans. Computer-Aided Design, vol. 8, no. 8, pp. 890–900, Aug. 1989.
-
(1989)
IEEE Trans. Computer-Aided Design
, vol.8
, Issue.8
, pp. 890-900
-
-
Sarrafzadeh, M.1
Lee, D.T.2
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