Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry

IEEE Journal of Solid-State Circuits

Volumn 30, Issue 4, 1995, Pages 432-435

  Tanaka, Satoshi ^b   Sasaki, Katsuro ^a  

^a HITACHI AMERICA LTD   (United States)

^b HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FREQUENCIES; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; LOGIC CIRCUITS; LSI CIRCUITS; SPEED; TECHNOLOGY;

CLOCK DRIVER; HALF SWING CLOCKING SCHEME; POWER CONSUMPTION; SPEED DEGRADATION; VOLTAGE SWING;

TIMING CIRCUITS;

EID: 0029291150     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.375963     Document Type: Article

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