A simple method for determining capacitive coupling coefficients in floating-gate devices

Solid State Electronics

Volumn 38, Issue 3, 1995, Pages 581-586

  Choi, Woong L ^a   Kim, Dae M ^a   Choi, I H ^b  

^a Pohang University of Science and Technology (POSTECH)   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; ELECTRIC CURRENT MEASUREMENT; PERFORMANCE; SUBSTRATES; THREE DIMENSIONAL;

CAPACITIVE COUPLING COEFFICIENT; CHANNEL LENGTH; CHANNEL WIDTH; DRAIN CURRENT; FLOATING GATE DEVICES; SUBTHRESHOLD SLOPE METHOD;

GATES (TRANSISTOR);

EID: 0029273480     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/0038-1101(94)00159-D     Document Type: Article

References (10)

1. Analysis and modeling of floating-gate EEPROM cells
2. Characterization and suppression of drain coupling in submicrometer EPROM cells
3. A scaleable technique for the measurement of intrinsic MOS capacitance with atto-Farad resolution