Implementation of a Digital Read/Write Channel with EEPR4 Detection

IEEE Transactions on Magnetics

Volumn 31, Issue 2, 1995, Pages 1180-1185

  Welland, Dave ^a   Phillip, Sandra ^b   Turtle, Tyson ^b   Leung, Ka ^b   Dupuie, Scott ^b   Holberg, Doug ^b   Jack, Randy ^b   Sooch, Nav ^b   Behrens, Rick ^b   Anderson, Kent ^b   Armstrong, Alan ^b   Bliss, Will ^b   Dudley, Trent ^b   Foland, Bill ^b   Glover, Neal ^b   King, Larry ^b  

^a Cirrus Logic   (United States)

^b Cirrus Logic   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; DATA ACQUISITION; INTERSYMBOL INTERFERENCE; MAGNETIC HEADS; SIGNAL PROCESSING; SIGNAL TO NOISE RATIO;

PARTIAL RESPONSE MAXIMUM LIKELIHOOD (PRML) SEQUENCE DETECTION;

MAGNETIC DISK STORAGE;

EID: 0029271313     PISSN: 00189464     EISSN: 19410069     Source Type: Journal    
DOI: 10.1109/20.364804     Document Type: Article

References (8)

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