A Coordinated Circuit Partitioning and Test Generation Method for Pseudo-Exhaustive Testing of VLSI Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 14, Issue 3, 1995, Pages 374-384

  Papachristou, Christos A ^b  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

^b CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; GRAPH THEORY; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; SHIFT REGISTERS;

BUILT IN SELF TESTING; COORDINATED CIRCUIT PARTITIONING; PSEUDO-EXHAUSTIVE TESTING; TEST GENERATION METHOD; TEST PATTERN GENERATION;

VLSI CIRCUITS;

EID: 0029267886     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.365128     Document Type: Article

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