A 4.4 ns CMOS 54 × 54-b Multiplier Using Pass-Transistor Multiplexer

IEEE Journal of Solid-State Circuits

Volumn 30, Issue 3, 1995, Pages 251-257

  Sasaki, Katsuro ^b   Shimizu, Akihiro ^a   Ohkubo, Norio ^a   Nakagome, Yoshinobu ^a  

^a HITACHI LTD   (Japan)

^b HITACHI AMERICA LTD   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; CRITICAL PATH ANALYSIS; DIGITAL ARITHMETIC; LOGIC DESIGN; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; MULTIPLEXING EQUIPMENT;

CARRY LOOKAHEAD ADDER (CLA); FORMANTISSA MULTIPLICATION; PASS TRANSISTOR MULTIPLEXERS;

MULTIPLYING CIRCUITS;

EID: 0029267856     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.364439     Document Type: Article

References (14)

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