The multiple-tunnel junction and its application to single-electron memory and logic circuits

Japanese Journal of Applied Physics

Volumn 34, Issue 2S, 1995, Pages 700-706

  Nakazato, Kazuo ^a   Ahmed, Haroon ^b  

^a HITACHI CAMBRIDGE LABORATORY   (United Kingdom)

^b UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

Logic; Memory; Semiconductor; Single electron; Tunnel junction

Indexed keywords

ELECTRONIC EQUIPMENT; ELECTRONS; FERMI LEVEL; LOGIC CIRCUITS; METALLORGANIC CHEMICAL VAPOR DEPOSITION; SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTOR DOPING; SEMICONDUCTOR STORAGE;

ELECTRON CHANNEL; LIQUID HELIUM TEMPERATURE; MULTIPLE TUNNEL JUNCTION; SIDE GATED CONSTRICTION; SINGLE CHARGE INJECTION LOGIC CIRCUIT; SINGLE ELECTRON MEMORY CELL; SINGLE ELECTRONICS;

TUNNEL JUNCTIONS;

EID: 0029255884     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.34.700     Document Type: Article

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