Short Papers On Correction of Multiple Design Errors

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 14, Issue 2, 1995, Pages 255-264

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; ERROR DETECTION; FINITE AUTOMATA; HEURISTIC METHODS; ITERATIVE METHODS; LOGIC DESIGN; MODIFICATION; SPECIFICATIONS;

CIRCUIT MODIFICATION; CORRECTION HARDWARE; LOGIC BLOCK; MULTIPLE DESIGN ERRORS; PAIRWISE DISTINGUISHING SEQUENCES; SINGLE ERROR CORRECTION SCHEME;

ERROR CORRECTION;

EID: 0029254567     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.370421     Document Type: Article

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