1 ns, 1 W, 2.5 V, 32 Kb, NTL-CMOS SRAM macro using a memory cell with p-channel access transistors

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 38, Issue , 1995, Pages

  Okamura, Hitoshi ^a   Toyoshima, Hideo ^a   Takeda, Koichi ^a   Oguri, Takashi ^a   Nakamura, Satoshi ^a   Takada, Masahide ^a   Imai, Kiyotaka ^a   Kinoshita, Yasushi ^a   Yoshida, Hiroshi ^a   Yamazaki, Toru ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; MOS DEVICES; THRESHOLD LOGIC; TRANSISTORS; VOLTAGE CONTROL;

NONTHRESHOLD LOGIC SRAM; STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0029254157     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)