0.18 μm CMOS hot-standby phase-locked loop using a noise-immune adaptive-gain voltage-controlled oscillator

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 38, Issue , 1995, Pages

  Mizuno, Masayuki ^a   Furuta, Koichiro ^a   Andoh, Takeshi ^a   Tanabe, Akira ^a   Tamura, Takao ^a   Miyamoto, Hidenobu ^a   Furukawa, Akio ^a   Yamashina, Masakazu ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DETECTOR CIRCUITS; ELECTRIC NETWORK ANALYSIS; PORTABLE EQUIPMENT; SIGNAL TO NOISE RATIO; TELECOMMUNICATION EQUIPMENT; TRANSFER FUNCTIONS; VARIABLE FREQUENCY OSCILLATORS;

FAST LOCK TIME; LOW JITTER; RECONFIGURABLE DELAY LINES; VOLTAGE CONTROLLED DELAY ELEMENTS;

PHASE LOCKED LOOPS;

EID: 0029254070     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)