50% active-power saving without speed degradation using standby power reduction (SPR) circuit

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 38, Issue , 1995, Pages 318-319

  Seta, Katsuhiro ^a   Hara, Hiroyuki ^a   Kuroda, Tadahiro ^a   Kakumu, Masakazu ^a   Sakurai, Takayasu ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC LOSSES; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; POWER SUPPLY CIRCUITS;

ACTIVE POWER DISSIPATION; POWER SUPPLY VOLTAGE; STANDBY POWER REDUCTION CIRCUIT; THRESHOLD VOLTAGE;

MOSFET DEVICES;

EID: 0029253931     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)