Built-in Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers

IEEE Transactions on Computers

Volumn 44, Issue 2, 1995, Pages 223-233

  Hellebrand, Sybille ^a   Rajski, Janusz ^b   Tarnick, Steffen ^c   Venkataraman, Snkanth ^d   Courtois, Bernard ^e  

^a UNIVERSITY OF SIEGEN   (Germany)

^b MENTOR GRAPHICS CORPORATION   (United States)

^c UNIVERSITY OF POTSDAM   (Germany)

^d UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^e TIMA LABORATORY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN TEST; HARDWARE TEST PATTERN GENERATORS; MULTIPLE-POLYNOMIAL LFSR; RESEEDING; SCAN DESIGN;

DATA COMPRESSION; POLYNOMIALS; SHIFT REGISTERS; VECTORS;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 0029252184     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.364534     Document Type: Article

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