Fast context switches: compiler and architectural support for preemptive scheduling

Microprocessors and Microsystems

Volumn 19, Issue 1, 1995, Pages 35-42

  Snyder, Jeffrey S ^a   Whalley, David B ^a   Baker, Theodore P ^a  

^a FLORIDA STATE UNIVERSITY   (United States)

Author keywords

context switches; preemptive scheduling; register remapping

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; PROGRAM COMPILERS; SHIFT REGISTERS;

CONTEXT SWITCHES; PREEMPTIVE SCHEDULING; REGISTER REMAPPING;

REAL TIME SYSTEMS;

EID: 0029251909     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/0141-9331(95)93086-X     Document Type: Article

References (13)

1. The effect of context switches on cache performance
2. Cache performance of operating system and multiprogram workloads
3. Flexible register management for sequential programs
4. Exploiting of context switches on cache performance
5. The interaction of architecture and operating system design
6. A portable global optimizer and linker
7. A design environment for addressing architecture and compiler interactions
8. Methods for saving and restoring register values across function calls
9. Fast context switches
10. RISC system/6000 power architecture
11. SPARC architecture to implementations