Sorting-Based VLSI Architectures for the M-algorithm and T-algorithm Trellis Decoders

IEEE Transactions on Communications

Volumn 43, Issue 234, 1995, Pages 514-522

  Bengough, Peter A ^a   Simmons, Stanley J ^b  

^a Bell Northern Research ^*  (United States)

^b QUEEN S UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTATIONAL COMPLEXITY; DECODING; DIGITAL COMMUNICATION SYSTEMS; ENCODING (SYMBOLS); ERROR CORRECTION; ITERATIVE METHODS; SEMICONDUCTOR DEVICE STRUCTURES; TRELLIS CODES;

DATA SEQUENCE ESTIMATION; INSERTION; ODD EVEN TRANSPOSITION; SORTING BASED VLSI ARCHITECTURE; WEAVESORTING TECHNIQUES;

VLSI CIRCUITS;

EID: 0029251579     PISSN: 00906778     EISSN: None     Source Type: Journal    
DOI: 10.1109/26.380070     Document Type: Article

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