The Modified Structure of the Lateral IGBT on the SOI Wafer for Improving the Dynamic Latch-up Characteristics

IEEE Transactions on Electron Devices

Volumn 42, Issue 2, 1995, Pages 367-370

  Sumida, Hitoshi ^b   Hirabayashi, Atsuo ^a   Kumagai, Naoki ^a  

^a FUJI ELECTRIC CO   (Japan)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CURRENT DENSITY; ELECTRIC CURRENT COLLECTORS; ELECTRIC CURRENTS; ELECTRIC LOADS; GATES (TRANSISTOR); PERFORMANCE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY;

FORWARD VOLTAGE DROP; INDUCTIVE LOAD; LATCH UP; WAFER;

BIPOLAR TRANSISTORS;

EID: 0029250039     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.370052     Document Type: Article

References (16)

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