A CMOS Low-Noise and Low-Power Charge Sampling Integrated Circuit for Capacitive Detector/Sensor Interfaces

IEEE Journal of Solid-State Circuits

Volumn 30, Issue 2, 1995, Pages 110-119

  Tedja, Suharli ^a,b   Van der Spiegel, Jan ^a   Williams, Hugh H ^a  

^a UNIVERSITY OF PENNSYLVANIA   (United States)

^b LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); ANALOG TO DIGITAL CONVERSION; CAPACITANCE; DETECTOR CIRCUITS; DIGITAL CONTROL SYSTEMS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CHARGE; ELECTRIC LOSSES; ELECTRONS; GATES (TRANSISTOR); SENSORS; SPURIOUS SIGNAL NOISE;

ANALOG STORAGE CELLS; CURRENT/CHARGE MODE AMPLIFIERS; DIGITAL CONTROL CIRCUITRY; SENSITIVE CHARGE PREAMPLIFIERS;

CMOS INTEGRATED CIRCUITS;

EID: 0029249216     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.341737     Document Type: Article

References (12)

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