Wafer mapping using DOE and RSM techniques

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 1995, Pages 289-294

  Walton, Anthony J ^a   Fallon, Martin ^a   Wilson, Dave ^a  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ANALYSIS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; COMPUTER SOFTWARE; GEOMETRY; MATHEMATICAL TECHNIQUES; MICROELECTRONICS; SELECTION;

CONTOUR PLOTS; CONTROL FACTORS; DESIGN OF EXPERIMENT TECHNIQUES; FACTORIALS; MEASUREMENT POINTS; RESPONSE SURFACE METHODOLOGY; THRESHOLD VOLTAGE; WAFER MAPPING; WAFER MAPS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0029237725     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)