New look at the conditions for the synthesis of speed-independent circuits

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1995, Pages 230-235

  Pastor, Enric ^a   Cortadella, Jordi ^a   Roig, Oriol ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; CONSTRAINT THEORY; ELECTRIC NETWORK SYNTHESIS; HAZARDS AND RACE CONDITIONS; LOGIC GATES; OPTIMIZATION; STATE ASSIGNMENT;

GATE LIBRARY; INTERNAL HAZARDS; MEMORY ELEMENTS; SPEED INDEPENDENT CIRCUITS;

LOGIC DESIGN;

EID: 0029230466     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)