Timing driven placement for large standard cell circuits

Proceedings - Design Automation Conference

Volumn , Issue , 1995, Pages 211-215

  Swartz, William ^a   Sechen, Carl ^a  

^a TimberWolf Systems Inc ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUIT; CRITICAL SIGNAL PATHS; LARGE STANDARD CELL INTEGRATED CIRCUITS; PARASITIC DELAYS; TIMING DRIVEN PLACEMENT; TIMING GRAPH; TIMING OPTIMIZATION ALGORITHM;

ALGORITHMS; CONSTRAINT THEORY; DELAY CIRCUITS; GRAPH THEORY; ITERATIVE METHODS; OPTIMIZATION; TIMING CIRCUITS;

INTEGRATED CIRCUITS;

EID: 0029226969     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.1995.250092     Document Type: Conference Paper

References (21)