Efficient approach for via minimization in multi-layer VLSI/PCB routing

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1995, Pages 473-476

  Cherng, Jong Sheng ^a   Chen, Sao Jie ^a   Tsai, Chia Chun ^a   Ho, Jan Ming ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; CONSTRAINT THEORY; ELECTRIC WIRING; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; PRINTED CIRCUIT BOARDS;

CHANNEL ROUTING ALGORITHMS; CONSTRAINED VIA MINIMIZATION; MULTILAYER VLSI/PCB ROUTING;

VLSI CIRCUITS;

EID: 0029225859     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)