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Volumn , Issue , 1995, Pages 42-47
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Power-profiler: optimizing ASICs power consumption at the behavioral level
a
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Author keywords
[No Author keywords available]
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Indexed keywords
CRITICAL PATH ANALYSIS;
CURRENT VOLTAGE CHARACTERISTICS;
GRAPH THEORY;
INTEGRATED CIRCUIT LAYOUT;
LOGIC DESIGN;
LOGIC GATES;
OPTIMIZATION;
PARALLEL PROCESSING SYSTEMS;
PERFORMANCE;
TIMING CIRCUITS;
BEHAVIORAL LEVEL;
BEHAVIORAL SYNTHESIS;
MIXED VOLTAGE CIRCUITS;
POWER CONSUMPTION;
POWER PROFILER;
APPLICATION SPECIFIC INTEGRATED CIRCUITS;
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EID: 0029225181
PISSN: 0738100X
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (71)
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References (12)
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