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Volumn , Issue , 1995, Pages 552-556
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On optimal board-level routing for FPGA-based logic emulation
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Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
APPLICATION SPECIFIC INTEGRATED CIRCUITS;
COMPUTATIONAL COMPLEXITY;
COMPUTER SIMULATION;
GRAPH THEORY;
ITERATIVE METHODS;
LOGIC CIRCUITS;
LOGIC GATES;
MICROPROCESSOR CHIPS;
OPTIMIZATION;
CHIP SIGNAL PINS;
ENTERPRISE EMULATION SYSTEM;
EULER CIRCUITS;
FIELD PROGRAMMABLE GATE ARRAYS;
LOGIC EMULATION SYSTEMS;
OPTIMAL BOARD LEVEL ROUTING;
REALIZER SYSTEM;
TIME OPTICAL ALGORITHMS;
COMPUTER AIDED LOGIC DESIGN;
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EID: 0029224151
PISSN: 0738100X
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/217474.217586 Document Type: Conference Paper |
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Times cited : (11)
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References (13)
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