Testability metrics for synthesis of self-testable designs and effective test plans

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1995, Pages 170-175

  Vahidi, Mahsa ^a   Orailoglu, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT IN SELF TEST; TESTABILITY METRICS;

CONSTRAINT THEORY; CORRELATION METHODS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; PERFORMANCE; PROBABILITY; VLSI CIRCUITS;

DIGITAL CIRCUITS;

EID: 0029223717     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)