Parallel algorithms for logic synthesis using the MIS approach

IEEE Symposium on Parallel and Distributed Processing - Proceedings

Volumn , Issue , 1995, Pages 579-585

  De, Kaushik ^a   Chandy, John A ^a   Roy, Sumit ^a   Parkes, Steven ^a   Banerjee, Prithviraj ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; INTERFACES (COMPUTER); ITERATIVE METHODS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; SYSTEMS ANALYSIS; VLSI CIRCUITS;

ASYNCHRONOUS MESSAGE DRIVEN COMPUTING MODEL; COMBINATIONAL LOGIC SYNTHESIS; DESIGN CYCLE TIME; LOGIC TRANSFORMATION; SEQUENTIAL ALGORITHM; SYNCHRONIZING BARRIERS;

PARALLEL ALGORITHMS;

EID: 0029218789     PISSN: 10636374     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)