Memory circuits for multiple valued logic voltage signals

Proceedings of The International Symposium on Multiple-Valued Logic

Volumn , Issue , 1995, Pages 52-57

  Current, K W ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; FLIP FLOP CIRCUITS; GATES (TRANSISTOR); MANY VALUED LOGICS; NEURAL NETWORKS;

HOLD CLOCK MODE; MEMORY CIRCUITS; MULTIPLE VALUED LOGIC VOLTAGE SIGNALS; SETUP CLOCK MODE;

LOGIC CIRCUITS;

EID: 0029218746     PISSN: 0195623X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)