Characterization and modeling of MOS mismatch in analog CMOS technology

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 1995, Pages 171-176

  Wong, Shyh Chyi ^a   Ting, Jyh Kang ^a   Hsu, Shun Liang ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC RESISTANCE; ELECTRIC VARIABLES MEASUREMENT; GEOMETRY; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DEVICE TESTING; TRANSCONDUCTANCE;

MISMATCH CHARACTERISTICS; TEST STRUCTURES;

MOS DEVICES;

EID: 0029218628     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)