Vision: an efficient parallel pattern fault simulator for synchronous sequential circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1995, Pages 221-226

  Nair, Rajesh ^a   Ha, Dong Sam ^a  

^a SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUITS; COMBINATIONAL LOGIC BLOCK; PARALLEL ITERATIVE SIMULATOR; PARALLEL PATTER FAULT SIMULATOR; SYNCHRONOUS SEQUENTIAL CIRCUITS;

COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; ELECTRIC FAULT CURRENTS; FAILURE ANALYSIS; FLIP FLOP CIRCUITS; HEURISTIC METHODS; ITERATIVE METHODS; LOGIC CIRCUITS;

SEQUENTIAL CIRCUITS;

EID: 0029213265     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)