DPCNN: a modular chip for large CNN arrays

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1995, Pages 417-420

  Salerno, M ^a   Sargeni, F ^a   Bonaiuto, V ^a  

^a UNIVERSITY OF ROME TOR VERGATA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; ELECTRIC CURRENTS; IMAGE PROCESSING; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; VLSI CIRCUITS;

DIGITALLY PROGRAMMABLE NEURAL NETWORKS; MODULAR CHIP; OUTPUT VOLTAGE;

NEURAL NETWORKS;

EID: 0029201388     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)