Measurements of the breakdown voltage of the lateral insulated gate bipolar transistor on the silicon-on-insulator film with varying implantation doses for the n-buffer layer

Japanese Journal of Applied Physics

Volumn 34, Issue 1, 1995, Pages 85-86

  Sumida, Hitoshi ^a   Hirabayashi, Atsuo ^a  

^a FUJI ELECTRIC CO   (Japan)

Author keywords

Blocking capability; Breakdown voltage; Implantation dose; LIGBT; N buffer layer; Punchthrough; SOI; Total charge

Indexed keywords

ELECTRIC BREAKDOWN OF SOLIDS; GATES (TRANSISTOR); ION IMPLANTATION; SEMICONDUCTING FILMS; SILICON ON INSULATOR TECHNOLOGY; VOLTAGE MEASUREMENT;

BLOCKING CAPABILITY; BUFFER LAYER; LATERAL INSULATED GATE BIPOLAR TRANSISTOR; PUNCHTHROUGH;

BIPOLAR TRANSISTORS;

EID: 0029196618     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.34.85     Document Type: Article

References (7)

1. H. Ohashi, J. Ohura, T. Tsukakoshi and M. Simbo: IEDM Tech. Dig. (IEEE, New York, 1986) p. 210.
2. H. Sumida and A. Hirabayashi: to be published in IEICE Trans. Electron.
3. I. Omura, N. Yasuhara, A. Nakagawa and Y. Suzuki: Proc. 5th ISPSD (IEEE, Monterey, 1993) p. 248.
4. T. Matsudai, Y. Yamaguchi, N. Yasuhara, A. Nakagawa and H. Mochizuki: Proc. 6th ISPSD (IEEE, Davos, 1994) p. 399.
5. A. Nakagawa, N. Yasuhara and Y. Baba: IEEE Trans. Electron Devices ED-38 (1991) 1650.
6. N. Yasuhara, T. Matsudai and A. Nakagawa: Ext. Abstr. 1993 Int. Conf. Solid State Devices and Materials (Business Center for Academic Societies Japan, Tokyo, 1993) p. 270.
7. H. Sumida, A. Hirabayashi and N. Kumagai: IEEE Trans. Electron Devices ED-41 (1994) 1301.