Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs

Proceedings of the International Symposium on Low Power Design

Volumn , Issue , 1995, Pages 33-38

  Monteiro, Jose ^a   Devadas, Srinivas ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC LOSSES; FINITE AUTOMATA; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; MATHEMATICAL MODELS; POWER ELECTRONICS; PROGRAMMABLE LOGIC CONTROLLERS;

FINITE STATE MACHINES; POWER ESTIMATION; USER SPECIFIED INPUT SEQUENCES;

SEQUENTIAL CIRCUITS;

EID: 0029192470     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/224081.224088     Document Type: Conference Paper

References (9)