Low-power multiplier design using delayed evaluation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 1995, Pages 1564-1567

  Sobelman, Gerald E ^a   Raatz, Donovan L ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CARRY LOGIC; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK TOPOLOGY; ENCODING (SYMBOLS); ENERGY DISSIPATION; SWITCHING;

CARRY PROPAGATE ADDER; CARRY SAVE ADDERS; POWER DISSIPATION;

MULTIPLYING CIRCUITS;

EID: 0029190792     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)