Reducing the frequency of tag compares for low power I-cache design

Proceedings of the International Symposium on Low Power Design

Volumn , Issue , 1995, Pages 57-62

  Panwar, Ramesh ^a   Rennels, David ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER ARCHITECTURE; LOGIC CIRCUITS; MICROPROCESSOR CHIPS;

BRANCH TAGGING; CACHE CONTROLLER; I CACHE; ON CHIP MEMORY; PREFETCH BUFFERS; S CACHE;

DATA STORAGE EQUIPMENT;

EID: 0029182643     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/224081.224092     Document Type: Conference Paper

References (7)