Highly parallel VLSI architectures for linear convolution

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 1995, Pages 1424-1427

  Elnaggar, A ^a   Alnuweiri, H M ^a   Ito, M R ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; COMPUTATIONAL METHODS; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK TOPOLOGY; MATHEMATICAL TRANSFORMATIONS; MATRIX ALGEBRA; MULTIPLYING CIRCUITS; PARALLEL PROCESSING SYSTEMS; TENSORS;

BIT SERIAL DEVICES; FACTORIZATION; LINEAR CONVOLUTION;

VLSI CIRCUITS;

EID: 0029181036     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)