Error correction algorithm for folding/interpolation ADC

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1995, Pages 700-703

  Kobayashi, Haruo ^a   Sakayori, Hiroshi ^a   Tobari, Tsutomu ^a   Matsuura, Hiroyuki ^a  

^a Teratec Corp   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CAPACITANCE; CODES (SYMBOLS); COMPARATOR CIRCUITS; COMPUTER SIMULATION; ERROR CORRECTION; FREQUENCIES; LOGIC CIRCUITS;

DIGITAL ERROR CORRECTION ALGORITHM; GRAY CODE; INTERPOLATION CIRCUIT;

ALGORITHMS;

EID: 0029180608     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)