Blocking voltage design consideration for deep trench MOS gate high power devices

IEEE International Symposium on Power Semiconductor Devices & ICs (ISPSD)

Volumn , Issue , 1995, Pages 256-260

  Matsushita, Ken'ichi ^a   Omura, Ichiro ^a   Ogura, Tsuneo ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC BREAKDOWN; GATES (TRANSISTOR); POWER ELECTRONICS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR JUNCTIONS; VOLTAGE MEASUREMENT;

BLOCKING VOLTAGE; BREAKDOWN VOLTAGE; DEEP TRENCH GATE DEVICE;

MOS DEVICES;

EID: 0029179066     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)