Mesh routing topologies for multi-FPGA systems

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1994, Pages 170-177

  Hauck, Scott ^a   Borriello, Gaetano ^a   Ebeling, Carl ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; COMPUTER AIDED NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC WIRING; LOGIC DESIGN; MICROPROCESSOR CHIPS; TREES (MATHEMATICS);

BIPARTITE GRAPHS; FIELD PROGRAMMABLE GATE ARRAYS; INTERCHIP DELAYS; MESH ROUTING TOPOLOGIES;

LOGIC GATES;

EID: 0028758203     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)