A video dsp with a macroblock-level-pipeline and a simd type vector-pipeline architecture for mpeg2 codec

IEEE Journal of Solid-State Circuits

Volumn 29, Issue 12, 1994, Pages 1474-1481

  Toyokura, Masaki ^a   Takeno, Hiroshi ^a   Akiyama, Toshihide ^a   Okamoto, Koyoshi ^a   Gion, Masahiro ^a   Minemaru, Takayuki ^a   Ohtani, Akihiko ^a   Araki, Toshiyuki ^a   Wilson, Brent ^a   Aono, Kunitoshi ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DECODING; ENCODING (SYMBOLS); ENERGY DISSIPATION; ESTIMATION; ITERATIVE METHODS; PIPELINE PROCESSING SYSTEMS; REAL TIME SYSTEMS; TECHNOLOGY; TRANSISTORS;

DISCRETE COSINE TRANSFORM; MACROBLOCK LEVEL PIPELINE; MOTION ESTIMATION; SINGLE INSTRUCTION MULTIPLE DATA STREAM; VECTOR PIPELINE ARCHITECTURE;

DIGITAL SIGNAL PROCESSING;

EID: 0028757657     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.340420     Document Type: Article

References (9)

1. K. Aono et al., “A video digital signal processor with a vector-pipeline architecture,” IEEE J. Solid-State Circ., vol. 27, no. 12, pp. 1886-1894, Dec. 1992.
2. S. K. Rao et al., “A real-time p64/MPEG video encoder chip,” ISSCC Dig. Tech. Papers, pp. 32-33, Feb. 1993.
3. D. Brinthaupt et al., “A video decoder for H.261 teleconferencing and MPEG stored interactive video applications,” ISSCC Dig. Tech. Papers, 34-35, Feb. 1993.
4. M. Nomura et al., “A 300 MHz 16b 0.5 pm BiCMOS digital signal processor core LSI,” IEEE J. Solid-State Circ., vol. 29, no. 3, pp. 290-297, Mar. 1994.
5. T. Demura et al., “A single-chip MPEG2 video decoder LSI,” ISSCC Dig. Tech. Papers, pp. 70-71, Feb. 1994.
6. M. Toyokura et al., “A video DSP with a macroblock-level-pipeline and a SIMD type vector-pipeline architecture for MPEG2 CODEC,” ISSCC Dig. Tech. Papers, 72-73, Feb. 1994.
7. T. Araki et al., “Video DSP architecture for MPEG2 CODEC,” Proc. ICASS P-94, vol. 2, 417-420, 1994.
8. T. Akiyama et al., “MPEG2 video codec using image compression DSP,” Dig. Tech. Papers of ICCE94, June 1994.
9. “Recommendation H.262 ISO/IEC 13818-2 draft international standard,” May 1994.