Simulation of a system level transient-induced latchup event

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 1994, Pages 193-199

  Lewis, Randall ^a   Minor, Joseph ^a  

^a WESTINGHOUSE ELECTRIC COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION; ELECTRIC RECTIFIERS; FAILURE ANALYSIS; FLIP FLOP CIRCUITS; NETWORK COMPONENTS; RELIABILITY; SIMULATION; SPACECRAFT; STRESS ANALYSIS;

ELECTRICAL OVERSTRESS DAMAGE; FUSED ALUMINUM BANDWIRE; PARASITIC SILICON CONTROLLED RECTIFIER; SYSTEM LEVEL TRANSIENT INDUCED LATCHUP FAILURE;

ELECTRIC NETWORK ANALYSIS;

EID: 0028757338     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)