Delay-verifiability of combinational circuits based on primitive faults

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1994, Pages 86-90

  Ke, Wuudiann ^a   Menon, P R ^a  

^a UNIVERSITY OF MASSACHUSETTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ERROR ANALYSIS; ERROR CORRECTION; THEOREM PROVING; TIMING CIRCUITS;

DELAY VERIFIABILITY; PATH DELAY FAULTS; PRIMITIVE FAULTS; VALIDATABLE NONROBUST TESTS;

COMBINATORIAL CIRCUITS;

EID: 0028755284     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)