1GDRAM cell with diagonal bit-line(DBL) configuration and edge operation MOS(EOS) FET

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1994, Pages 639-642

  Shibahara, K ^a   Mori, H ^a   Ohnishi, S ^a   Oikawa, R ^a   Nakajima, K ^a   Kojima, Y ^a   Yamashita, H ^a   Itoh, K ^a   Kamiyama, S ^a   Watanabe, H ^a   Hamada, T ^a   Koyama, K ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITOR STORAGE; CAPACITORS; CELLULAR ARRAYS; DIELECTRIC FILMS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; OPTIMIZATION; SEMICONDUCTOR DEVICE STRUCTURES; TANTALUM COMPOUNDS; VOLTAGE CONTROL;

CAPACITOR OVER BIT LINE; DIAGONAL BIT LINE;

RANDOM ACCESS STORAGE;

EID: 0028755084     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)