Dual polycide gate and dual buried contact technologies achieving a 0.4 μm nMOS/pMOS spacing for a 7.65 μm2 full-CMOS SRAM cell

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1994, Pages 855-858

  Koike, H ^a   Unno, Y ^a   Ishimaru, K ^a   Matsuoka, F ^a   Kakumu, M ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHOUS MATERIALS; DIFFUSION IN SOLIDS; ELECTRIC CONTACTS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; RANDOM ACCESS STORAGE; SEMICONDUCTING SILICON; SEMICONDUCTOR DOPING; SEMICONDUCTOR GROWTH;

DUAL BURIED CONTACT; DUAL POLYCIDE GATE;

CMOS INTEGRATED CIRCUITS;

EID: 0028753663     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)