High-level synthesis methodology for low-power VLSI design

IEEE Symposium on Low Power Electronics

Volumn , Issue , 1994, Pages 48-49

  Goodby, Laurence ^a   Orailoglu, Alex ^a   Chau, Paul M ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK SYNTHESIS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; PIPELINE PROCESSING SYSTEMS;

LIBRARY BASED DESIGN STYLE; LOW POWER DESIGN; MODULE SELECTION; SIERRA HIGH LEVEL SYNTHESIS SYSTEM;

VLSI CIRCUITS;

EID: 0028746457     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)